The flash EEPROM (Electrically Erasable Programmable Read Only Memory) device is an advanced type of EEPROM which can be erased electrically in high speeds without being removed from the circuit board. Prior to reprogramming, the conventional EPROM (Electrically Programmable Read Only Memory) device must be removed from the circuit board and exposed to ultraviolet light for about 20 minutes in a special apparatus in order to be erased. As the flash EEPROM does not need such a time consuming erase procedure, it is more convenient to use. Also, the flash EEPROMs can cost less than the EPROMs since they do not require the costly erase handling and the time delays for the erasure in the mass production environment, and do not use the expensive quartz-window ceramic packages commonly used in EPROMs. Despite these advantages over EPROMs, the prior art EEPROMs had several disadvantages, such as large chip size and the over-erase problem. Therefore, constant improvements had been made for prior art EEPROMs with different approaches and implementations, which include stacked gate cells, two-transistor cells, split gate cells, source side injection cells, and other types of EEPROM cells.
The first stacked gate EEPROM cell implemented in a single transistor was disclosed by Frohman-Bentchkowsky et al. in U.S. Pat. No. 4,203,158 issued May 13, 1980. This cell consisted of a double-poly stacked gate structure with a thin oxide area which was used for both erasing and programming by the Fowler-Nordheim tunneling phenomenon. Another stacked gate cell was proposed by Mukherjee et al. in U.S. Pat. No. 4,698,787 issued Oct. 6, 1987. The Mukherjee prior an cell shown in FIG. I employs the channel hot electron injection for the programming at the drain side, and Fowler-Nordheim tunneling for erasing at the source side. Although the stacked gate cell results in a minimum cell size comparable to the conventional EPROM cell, it has a major disadvantage called the over-erase problem.
The over-erase problem occurs in stacked gate cells when the floating gate in FIG. 1 is overly discharged during the erase operation. The threshold voltages of over-erased cells are negative and such cells conduct current even when they are not selected by a read voltage applied to the control gate. If one or a few of the cells in a column (or row) of the cell array were over-erased and constantly conducting leakage currents, then the whole column (or row) of the cells will have malfunctions because the sense amplifier can not detect the correct data from the selected cell in the column (or row).
In order to get around this over-erase problem, the stacked gate EEPROM devices are usually erased by a time consuming iteration algorithm instead of being erased at once. During the erase operation, such an iteration algorithm will read and test out each byte of cells in order to make sure that cells are not over-erased after each small incremental step of erasing is performed. This iteration is repeated until all the cells in the device are properly erased. Presently a commercial one mega bit flash EEPROM device having the stacked gate cells takes more than 2 seconds for erasing, or a minimum of 5 seconds for erasing and reprogramming due to the time consuming iterative erasure. Because of such a slow reprogram time, the stacked gate Flash EEPROM devices can only be used in applications where the reprogramming of the device is infrequent. The stacked gate EEPROM devices are not suitable for high speed applications like hard disk drive replacements, where 10 to 20 milliseconds of much faster erase time is required.
In order to solve the over-erase problem, two different types of EEPROMs have been introduced. One type of EEPROM employs a two-transistor cell structure which was disclosed by Periegos in U.S. Pat. No. 4,558,344 issued Dec. 10, 1985. Another type of EEPROM cell employs a single transistor called the split gate, and one such cell was disclosed by Samachisa et al. in U.S. Pat. No. 4,783,766 issued Nov. 8, 1988.
The two-transistor EEPROM cell of Periegos shown in FIG. 5 solved the over-erase problem and several other problems inherent to the stacked gate cell. The Perlegos prior art employs a select gate 54 and a tunneling window 57 of thin oxide. Electrons are tunneled through tunneling window 57 between a floating gate 55 and a substrate 50 by the Fowler-Nordheim tunneling for both programming and erasing of floating gate 55. Select gate 54 in the Periegos cell blocks the leakage current from over-erased floating gate 55 when the cell is not selected, and eliminates the over-erase related drawbacks. However, the major disadvantage of Perlegos prior art was the big cell size. Perlegos cell occupied about four times larger area than stacked gate cells, increasing the chip size and the cost accordingly. Another Perlegos cell shown in U.S. Pat. No. 4,701,776 (issued Oct. 20, 1987) reduced the cell area by a half of his prior art cell, but the size of cell area still remained more than twice the size of stacked gate cells. The two-transistor EEPROM devices are usually manufactured in relatively low densities due to their large cell size and relatively high cost.
The split gate EEPROM cell of Samachisa et al. shown in FIG. 2 also solved the over-erase and other problems related to the stacked gate cells, while reducing the cell size to about a half of the two-transistor EEPROM cell size. This was achieved by a combination of a storage transistor (55 and 56 in FIG. 5) and a select transistor (54 in FIG. 5) in the two-transistor EEPROM cell into one single transistor having two split channels under a control gate 24 as shown in FIG. 2. The "select gate portion" of a channel 25 between a source 21 and a point 20a below control gate 24 has the function of blocking the leakage current coming from the "floating gate portion" of channel 25 between a point 20b and a drain 22 under an over-erased floating gate 23, when control gate 24 is turned off. As there are no concerns about the over-erase problem, the split gate EEPROM devices can be erased at a full potential speed which takes only 10 to 20 milliseconds to erase a full chip in densities of millions of bits. The erasure of the split gate cell is accomplished by the Fowler-Nordheim tunneling from floating gate 23 to control gate 24, to drain 22, or to the erase gate (not shown) depending on the implementations. The programming of the split gate cell is accomplished by the conventional channel hot electron injection at a drain junction 20c as in the stacked gate cells.
A number of different variations of split gate cells have been introduced so far. Examples of such split gate EEPROM cells are shown by Miccoli et al. in U.S. Pat. No. 4,412,311 issued Oct. 25, 1983, by Samachisa et al. in U.S. Pat. No. 4,783,766 issued Nov. 8, 1988, by Eitan in U.S. Pat. No. 4,795,719 issued Jan 3, 1989, by Lu et al. in U.S. Pat. No. 5,036,378 issued July 30, 1991, and by Harari in U.S. Pat. No. 5,095,344 issued May 10, 1992. Each of these prior arts attempted to solve new problems found in the split gate cells, or added new improvements.
In theory, the split gate EEPROM devices looked easy to manufacture with only 30 percent larger size than a stacked gate cell, but actual production of split gate device was not easy because the split gate cell was very sensitive to the mask misalignments which usually occurred in the manufacturing environment. Referring back to FIG. 2, if the masks are misaligned during the manufacturing, the "select gate portion" of control gate 24 may be made substantially smaller than the "floating gate portion" of control gate 24, or vice versa, when control gate 24 itself has a minimum allowed dimension. As a result, there were severe batch-to-batch variations in the performance of split gate EEPROMs. In order to overcome such manufacturing difficulties, the Samachisa prior an and the Eitan prior an incorporated the self-align process technique widely used in EPROM manufacturing. The name of "flash EEPROM" originated from the description by Masuoka et al. in 1984 IEDM Technical Digest, p. 464 in an article titled "A new flash EEPROM cell using triple polysilicon technology". The Masuoka prior an incorporated a separate erase gate within each of the split gate cells and connected all the erase gates with same wire, thus all cells could be erased at once in a flashy speed. However, the Masuoka cell had disadvantages of a large cell size and sensitivity to mask misalignment. Disadvantages of the Masuoka prior art have been overcome by Lu et al. in U.S. Pat. No. 5,036,378 issued July 30, 1991, and by Harari in U.S. Pat. No. 5,095,344 issued May 10, 1992. The Lu and Harari prior arts incorporated the buried diffusion, self-align techniques, and new erase gate structures in order to have a reduced cell size and improved manufacturability.
Still, the major drawbacks of split gates are the low programming efficiency and the use of relatively high drain voltages during the programming. Most prior art split gate cells are programmed by the conventional channel hot electron injection method which has a very low programming efficiency. It is well known in the art that generally less than 0.000005 percent of the source-to-drain current is actually injected into the floating gate during the programming. Such low injection efficiency unnecessarily wastes power and prohibits faster programming. Presently, split gate EEPROMs are required to apply 8 to 9 volts to the drain and 12 volts to the control gate during the programming, while the chip power supply voltage is only 5 volts. Since the control gates do not conduct DC currents during the programming, the size of the 12-volt charge pump can be made relatively small. However, a relatively large size charge pump is required to generate the high drain voltage from the 5-volt power supply because a large amount of DC current will flow between the source and the drain of each cells during the programming. The use of a high voltage at the drain also requires a high voltage endurance junction for the drain in order to prevent the punch-through and the junction breakdown problems. The high voltage junction not only results in a larger cell area and a larger chip size, but also makes the fabrication process difficult to scale down.
An attempt to improve the efficiency of hot electron injection to the floating gate has been made by Wu et al. as disclosed in U.S. Pat. No. 4,794,565 issued Dec. 27, 1988. The preferred embodiment of the Wu prior art shown in FIG. 3 includes a second vertical floating gate called a side wall gate 35 at the source side of conventional stacked gate structure in order to induce the hot electron injection from a source 31 when a control gate 34 is applied with a high voltage. This type of hot electron injection is called the source side injection (SSI) phenomenon in the art. The source side injection phenomenon was discovered from the earlier researches on the undesirable gate currents in the MOS transistor, in which the source region implant was slightly misaligned to create a gap between the source and the gate. Wu et al. compared the performances of source side injection and conventional channel hot electron injection in their patent and in an article of 1986 IEDM p. 584, entitled "A Novel High-Speed 5-Volt Programming EPROM Structure". Also, Naruke et al. recreated the Wu prior art with a slight modification and reported in 1989 IEDM p. 603 in an article titled "A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side". Although both articles reported drastic improvements of hot electron injections in the source side injection by 1,000 to 10,000 times compared to the conventional channel hot electron injection, they could not explain exactly how such improvement had occurred. Mar et al. introduced another modified source side injection cell in U.S. Pat. No. 5,280,446 issued Jan. 18, 1994. Besides the high programming efficiency, Wu, Naruke, and Mar prior arts have an additional advantage of using relatively low drain voltages for the programming operation.
Even though Wu, Naruke, and Mar prior arts have the same basic cell structure for the source side injection mechanism, they can be differentiated by the method of connecting the side wall gate. In the case of the Wu prior art in FIG. 3, side wall gate 35 is made to float. Floating side wall gate 35 couples the "weak gate control" voltage from control gate 34. The coupled voltage of floating side wall gate 35 can shift widely depending on the process variations. Also, floating side wall gate 35 can be negatively charged by the accumulation of stray electrons after thousands of programming cycles. Since there is no path to discharge the accumulated negative charges from floating side wall gate 35, the negative voltage of floating side wall gate 35 can permanently turn off the channel below, and the cell will eventually become nonfunctional. In the case of the Naruke prior art, side wall gate 35 in FIG. 3 is not floating. Instead, it is extended in side ways (perpendicular to the cross-sectional view in FIG. 3 ) to work as a word line connector between the cells. Now, a stable voltage can be enforced to side wall gate 35 by the word line connection. Since the polysilicon side wall gate is narrowly formed by a destructive formation called the RIE (Reactive Ion Etching) process, such a long word line of narrow side wall will have a very high electrical resistance. Also, it is not convenient to make connections from the metal lines to such narrow polysilicon side wall lines. The Mar prior an improved the drawback of the Naruke prior art by running the word line connection of the side wall gate in a perpendicular direction to that of the Naruke prior art. The word line connection of a select gate 45 in FIG. 4 of the Mar prior art runs in a direction from a source 41 to a drain 42. Due to this polysilicon word line passing over source 41 and drain 42, the metal line connections can not be made directly to source 41 or drain 42. Hence, multiple cells have to share a long source connection and a long drain connection. Consequently, the read speed of the Mar prior an will be significantly slower than other prior arts due to the high resistance of the long diffusion lines.
Besides the individual drawbacks mentioned above, the Wu, Naruke, and Mar prior arts have five common disadvantages: the false read problem, the program disturb problem, the insufficient margin of the select gate voltage, the process sensitivity, and the need of a low voltage generator.
First, these source side injection prior arts have the false read problem related to the same over-erase problem commonly found in the stacked gate cells, due to the lack of a proper select gate. It is well known in the an that short channel gates tend to have severe sub-threshold leakage currents, especially when the gates are in sub-micron dimensions. Side wall gate 35 in FIG. 3 used as a select gate is as thin as the thickness of gate polysilicon, and is much narrower than the length of a floating gate 33 which already has a minimum sub-micron dimension at the present time. Therefore, a significant amount of sub-threshold leakage current will flow between source 31 and a point 30b on a channel 36 even when side wall gate 35 is turned off, if floating gate 33 is over-erased and conducting. As multiple cells share a common bit line and the leakage currents from each cell will add up, the substantial sum of combined leakage currents will cause a malfunction of the sense amplifier, resulting in a false data read from the selected cell and causing a significant device reliability problem. The same situation can happen in the Mar prior art because the distance between an edge 40a and a point 40b in FIG. 4 is also relatively shorter than the standard minimum gate length of floating gate 43. In order to get around the false read problem caused by the over-erased floating gate and the leaky select gates, the source side injection EEPROM device must use the time consuming iterative erase algorithm commonly used in the stacked gate EEPROM devices. As a result, the erase time will take several seconds for the source side injection EEPROM devices.
Second, the sub-threshold leakage current of the side wall (or select) gate mentioned above results in another reliability problem called the program disturb in the source side injection EEPROM devices. During the program operation, side wall gate 35 in FIG. 3 and select gate 45 in FIG. 4 of the source side injection cells are usually biased just slightly above the threshold voltage or are almost turned off in order to maximize the programming efficiency. For the programming of the Naruke prior art cell, side wall gate 35 is applied with only 1.5 volts whereas its threshold voltage is about 1 volt. As compared to the 5 volts of side wall gate voltage during the read operation, side wall gate 35 is operating in an almost turned-off state during the programming. What that means is that the source side injection needs only a small amount of the source-drain current for the programming. Now, if there are leakage currents through the side wall (or select) gate in the unselected (turned off) cells which share the same control line as the selected (to be programmed) cell, then these unselected cells will also have small but significant amount of electrons injected into the floating gate due to the high control gate voltage applied while the selected cells are being programmed. If the programming is repeated for other blocks of cells which share the same control line, unselected cells with the leaky side wall (or select) gate will be eventually programmed to contain wrong data. Therefore, this program disturb phenomenon is a serious reliability problem for the source side injection EEPROMs.
Third, the side wall (or select) gate voltages used for the programming of the source side injection cells do not have sufficient noise margins. The Naruke prior art uses 1.5 volts and the Mar prior art uses 2 volts for the side wall (or select) gate during the programming. The floating side wall gate of the Wu prior art is assumed to have a similar level of voltage which is capacitively coupled from the control gate during the programming. As compared to the 1-volt threshold voltage and the 5-volt power supply voltage, the 1.5 volts and 2 volts do not give enough noise margin for the side wall (select) gate. The voltage fluctuations and the noise glitches on the power supply line and the ground line will undesirably turn on the unselected gates or turn off the selected gates due to the relatively small voltage margins. Since the side wall (select) gate is operating in the linear region of the transistor transfer curve at such a low bias, a small amount of noise will be amplified to cause substantial fluctuations in the source-to-drain current and will result in undesirable electron injections to the floating gates of the unselected cells. Therefore, it is not safe to use the source side injection EEPROM devices having such low voltage margins in the ordinary environments, where the noises are quite common.
Fourth, since the electron injection area is located very close to the source, the functionality of the source side injection is very sensitive to the variations in the manufacturing process. Due to the fact that the select gate is operating in the very sensitive linear region, slight changes in the process parameters will cause substantial variations in the performance of the source side injection devices. If the channel length of the narrow select gate (the distance between edge 40a and point 40b FIG. 4) is slightly increased due to a process variation, then the programming efficiency and speed will drop substantially due to a drastic reduction of carriers, as the select gate voltage is kept at the same low level. If the doping level of the channel is slightly increased, then the increased select gate threshold voltage will substantially reduce the programming efficiency. Also, since the side wall gate and select gate are narrow devices, a slight reduction in the channel length between an edge 30a and a point 30b in FIG. 3 (also, between edge 40a and point 40b in FIG. 4) will drastically increase the sub-threshold leakage current, which will seriously affect the program disturb and the false read problems mentioned above. Hence, manufacturing of such devices with consistent results and scaling of the process would be very difficult.
Fifth, the Naruke and Mar prior arts require low voltage generators in order to provide 1.5 volts and 2 volts for the side wall (select) gates from the 5-volt power supply voltage. If the low voltage generator circuit is not carefully designed, the process variations and the operating temperature variations will significantly impact the accuracy of the low voltage and in turn will significantly affect the programming efficiency and speed.
In a conclusion, the source side injection prior arts mentioned above are not easy to manufacture, are not easy to scale, and are not reliable to use due to the false read problem, the program disturb problem, the noise sensitivity, and the process sensitivity which are caused by the proximity of the electron injection area to the source, even though the programming efficiency is very high.
Yeh proposed in U.S. Pat. No. 5,029,130 issued Jul. 2, 1991 that a split gate similar to the one in FIG. 2 could generate a carrier injection similar to the source side injection if he would use a different programming bias compared to the split gate embodiment proposed by the Wu prior art patent. But it is still believed that the conventional hot electron injection at the drain is more dominant than the source side injection in his cell because a very high drain voltage is used. It is well known that the source side injection does not use a high voltage at the drain during the program. As in the Miccoli prior art, the Yeh split gate cell uses a drain-to-gate coupling to obtain a high floating gate voltage for the channel hot electron injection Such a coupling is known in the art to cause undesirable punch-through failures and leakage currents due to a very high voltage at the drain. The Yeh split gate cell also employs a pointed floating gate for enhanced poly-to-poly erasure between the floating gate and the control gate. The pointed floating gate is not easy to scale and is not easy to reproduce consistently in the mass production environment, because the size of polysilicon granule is not consistent. Disadvantages of Yeh prior art include the use of very high voltage at the drain, a large overlap area between the floating gate and the drain, susceptibility to punch-through failure, sensitivity to drain voltage, and difficulties in manufacturing and process scaling.